NCP1578MNR2G【PDF 17/22 页】IC REG DL BCK/LINEAR SYNC 20-QFN

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NCP1578

http://onsemi.com

GENERAL APPLICATION INFORMATION

Introduction

Figure 35 depicts the general control blocks of voltage

mode control loop for a synchronous-rectified buck

converter. The voltage output V

out

is regulated to a reference

level which is basically governed by the following formula

out

(eq. 1)

In order to provide proper regulation, the error amplifier is

compared with the internal reference voltage and the output

of the error amplifier is used to provide pulse-width

modulated (PWM) wave.

Loop Compensation

Since NCP1578 is a voltage mode PWM controller with

LC output filter, type III compensation network is

recommended to provide the good closed loop bandwidth

and phase boot with stability under any circumstances. The

purpose of compensation is to obtain a stable close loop

system with the highest possible bandwidth. In another

word, we need to obtain a fast and stable system.

SWN

VOUT

PGND

COMP

PWM Logic

Gate Driver &

Ramp Generator

Vref

Error

Amp

VIN

CIN

DCR

ESR

COUT

NCP1578

Output

Filter

Compensation

Network

Modulator

Figure 35. Buck Converter with Modulator, Output Filter and Compensation Network

Equations Involved in Compensation Network

The following equations are provided as general

guidelines for defining the positions of poles and zeros of the

compensation network.

Output Filter Break Frequency

2p L C

out

(LCDoublePole)

(eq. 2)

ESR

2p ESR C

out

(ESRZero)

(eq. 3)

Compensation Network Break Frequency

2p R3 C2

(1stZero)

(eq. 4)

2p R3

C1 C2

C1)C2

(1stPole)

(eq. 5)

2p (R1)R4) C3

(2ndZero) (eq. 6)

2p R4 C3

(2ndPole)

(eq. 7)

Guidelines for selecting compensation component

1.Select a value of R1 between 2 kW and 5 kW

2.Target for close loop bandwidth should be less

than 50% of switching frequency

3.Place 1

zero at 50% of filter double pole.

4.Place 1

pole at ESR zero

5.Place 2

zero at filter double pole

6.Place 2

pole at half the switching frequency.

Figure 36 shows an asymptotic plot of the converter gain

against frequency. It gives the general trend of how system

and its individual components behave. Actually, the

Modulator and Filter Gain has a high peak due to the high Q

factor of the output filter. The Open Loop Error Amplifier

Gain bounds the Compensation Gain. The Converter Gain

is constructed on the graph by summing up the Modulator

and Filter Gain (in dB) and the Compensation Gain (in dB).

The Compensation Gain uses the external impedance

network (R1, R4, C3, C1, C2, R3 at Figure 35) to provide a

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